Where this was said
Building a multiply-accumulate from logic gates
At 15:10 · chapter starts 0:00
Reiner explains why multiply-accumulate is the fundamental AI chip operation. Demonstrates partial product generation with AND gates and introduces the DADA multiplier using full adders (3-to-2 compressors). Area scales as p×q. [1] — Reiner Pope "The fundamental AI chip operation — multiply-accumulate — requires exactly p×q AND gates to generate partial products, then p×q full adders…" 03:28
The fundamental AI chip operation — multiply-accumulate — requires exactly p×q AND gates to generate partial products, then p×q full adders (3-to-2 compressors) to sum them in a DADA tree. Every atomic step in long multiplication maps directly to a physical logic gate. This is why area scales quadratically with bit width.
A p-bit by q-bit integer multiplier requires exactly p×q AND gates to generate partial products, scaling quadratically with bit width.
A DADA multiplier uses p×q full adders because each full adder eliminates one bit from the partial product tree, reducing 24 input bits to 8 output bits.
Multiplier circuit area scales quadratically with bit width, so halving precision from FP8 to FP4 should yield 4× more throughput. NVIDIA historically reported only 2×. The B3-100 finally moved to 3×, but the theoretical max is 4×. This quadratic scaling is the single biggest reason low-precision AI arithmetic works so well.
Halving the bit precision of a multiplier reduces circuit area quadratically, meaning FP4 should theoretically be 4× faster than FP8, not 2×.
Starting with the B3-100, NVIDIA began acknowledging the quadratic scaling and now specs FP4 at 3× the throughput of FP8, though the theoretical maximum is 4×.
