Where this was said
FPGAs vs ASICs
At 1:03:58 · chapter starts 53:25
Contrasts FPGAs (reprogrammable, $10K first cost) with ASICs (~$30M tape-out, 10× more efficient). Explains LUT internals as truth-table-based MUXes, showing why FPGAs have ~10× overhead. [1] — Reiner Pope "An FPGA emulates any circuit using lookup tables (LUTs) and programmable MUXes, but each 4-input LUT costs ~32 gate-equivalents to implemen…" 52:00
An equivalent FPGA implementation costs approximately 10× more in silicon area and energy than a dedicated ASIC, because each programmable LUT uses ~32 gates to implement what an ASIC does with ~3.
A CPU cache lets hardware silently decide whether to fetch from fast on-chip memory or slow DDR — introducing non-deterministic latency. A TPU scratchpad gives software explicit instructions for on-chip versus HBM memory. The cache gives 100× faster access on a hit, but the non-determinism is the price.
