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Clock cycles and pipeline registers
At 39:50 · chapter starts 39:11
Explains why a global clock synchronizes all chip circuitry every ~nanosecond. Pipeline registers can halve logic depth and double clock speed. Feedback loops (running sums) create the hardest timing constraints. [1] — Reiner Pope "A chip's global clock forces every transistor to synchronize in lockstep every nanosecond. Without it, two paths through logic could produc…" 39:20
A chip's global clock forces every transistor to synchronize in lockstep every nanosecond. Without it, two paths through logic could produce outputs that arrive at different times, corrupting results. Pipeline registers let you split logic to raise clock speed, but a feedback loop in the adder shows the hard limit: you can't pipeline your way out of a recurrence.
A chip's global clock synchronizes all circuitry in lockstep approximately every nanosecond, enabling coordination across 100 billion transistors.
Splitting a logic cloud with a pipeline register in the middle allows the chip to run at twice the clock frequency, at the cost of additional register area.
An FPGA emulates any circuit using lookup tables (LUTs) and programmable MUXes, but each 4-input LUT costs ~32 gate-equivalents to implement what an ASIC does with ~3 gates. That's the source of the ~10× area and energy penalty. The trade-off: first ASIC costs $30M in tape-out; first FPGA costs $10K.
The first manufactured ASIC requires a full tape-out costing around $30 million, while the first FPGA costs roughly $10,000, making FPGAs ideal for frequently changing designs.
