A TPU has a few large systolic arrays (MXUs) with a shared vector unit. A GPU is the same architecture tiled many times in miniature: each SM has a Tensor Core (mini-MXU) plus its own vector unit. The GPU trades larger systolic array amortization for more parallel data paths between vector and matrix units.
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At 1:18:20 · chapter starts 1:18:15
TPU has few large systolic arrays with shared vector units. GPU tiles many miniaturized versions across the chip — each SM is a tiny TPU. GPUs trade large-array amortization for more parallel data paths. [1] — Reiner Pope "A TPU has a few large systolic arrays (MXUs) with a shared vector unit. A GPU is the same architecture tiled many times in miniature: each …" 1:18:20
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